Machine implementable page or other fixed block replacement methods have been used to control the movement of pages (fixed blocks) and to affect the dynamic association between the logical address space and the physical address space of a storage hierarchy. Relatedly, it is art recognized that a hierarchical storage system having a least recently used (LRU) or most recently used (MRU) page replacement policy requires a substantially smaller number of pages (fixed blocks) subject to an accessible demand paging regimen than a single-level store. The performance of caches (directory managed buffered stages) is characterized by hit/miss ratios. A "hit" means that a READ reference to the cache generated by a requesting CPU executable process locates the data item it desires in the high-speed cache, rather than in a lower speed backing store. A "hit" with respect to a WRITE reference is made when the CPU executable process through the cache manager finds a counterpart location in a partially full buffer to overwrite. In this regard, a "miss" is registered if the data is unavailable in cache with respect to a READ reference, or, if an item must be destaged from the cache in order to make room for a WRITE reference.
If data must be destaged or staged up between the small high-speed cache and the larger, but slower backing store, staging algorithms are required. Popular algorithms, such as LRU or MRU, maintain in the cache inventory those items which, more likely than not, will be referenced by a CPU executable process in the future. A cache not containing a referenced item and otherwise full must remove one of its data elements so that it can be replaced by the requested item. Thus, a system tries to replace the least recently referenced item under the assumption that items which have not been referenced for a long time will not likely be referenced in the future.
A disk cache is a cache or buffer used to hold portions of the disk address space contents. It differs from a CPU cache by its physical location within the storage subsystem and its responsiveness to channel command words.
In operation, when a CPU executing process references information not stored within its CPU cache or main memory, reference is made to a storage subsystem external to the CPU. In the prior art as for example in Clark et al, U.S. Pat. No. 3,725,864, "Input/Output Control" and Luiz et al, U.S. Pat. No. 4,207,609, "Path Independent Device Reservation and Reconnection in a Multi-CPU and Shared Device Access System", there is described the transfer of data to and from a CPU and the accessed locations of storage devices. Such systems employ a physical path connection involving a channel, a control unit communicating with the channel on one side in an asynchronous relationship and selected devices on the other side. The operating system of the CPU initiates the transfer by a START I/O instruction. This causes control to be relinquished to a series of channel command or command words (CCW's). A sequence or chain of channel commands is, in turn, sent from the CPU over the channel to the control unit for selecting and accessing the storage device as well as effectuating the data movement across the interface. Both the Clark and Luiz patents also describe the adaptive disconnection and reconnection of channels and devices thereby making the CPU and device association path independent.
Caches in the form of either associative or random access memory have access times in nanoseconds whereas DASD's have access times in terms of milliseconds. By locating a LRU/MRU managed cache within a DASD storage control unit, there exists an expectation that a high hit ratio of CCW references would substantially increase throughput. This derives from the fact that most of the references are answered in microseconds while only a minority must take the milliseconds required for staging from DASD to cache.
In current designs for DASD cache, when a cache "miss" occurs, the record stored on a DASD track required by the reference plus all the records following that record on the same track are staged to the cache buffer. In this regard, the conventional unit of data management within the cache is the DASD track. This is convenient because DASD tracks are of equal size although the records contained therein may be of different sizes.
The pertinent prior art includes Niguette et al, U.S. Pat. No. 3,938,097, "Memory and Buffer Arrangement for Digital Computers", issued Feb. 10, 1976; Nelson, U.S. Pat. No. 3,541,529, "Replacement System", issued Nov. 17, 1970; Bardesley et al, U.S. Ser. No. 362,827, "Address Control of Fragmented Buffer Spaces Byte Synchronized with Streamed Records", filed Mar. 29, 1982, now abandoned; and Easton et al, "Use Bit Scanning in Replacement Decisions", 28 IEEE Transactions on Computers, pp. 133-141, February 1979. For a state-of-the-art view of CPU caches, reference should be made to Computing Surveys, Volume 14, No. 3, September 1982, pp. 473-530.